SCL (Source Coupled Logic) circuits are known as a kind of current mode logic circuits capable of performing low-amplitude and high-speed operation. FIG. 1 is a circuit diagram showing the clock buffer circuit that employs a conventional SCL circuit. Referring to FIG. 1, NMOS transistors MN1 and MN2 are transistors that constitute a differential stage. Load resistances R1 and R2 are connected to the drain electrodes of these transistors and a VDD power supply, respectively. An NMOS transistor MN3 is connected between the source electrodes of the NMOS transistors MN1 and MN2 and a VSS power supply. An NMOS transistor MN4 and a resistance R3 constitute a bias current. The drain electrode of the NMOS transistor MN4 is connected to the gate electrode of the NMOS transistor MN4. The source electrode of the NMOS transistor MN4 is connected to the VSS power supply. One end of the resistance R3 is connected to the drain electrode of this transistor, and the other end of the resistance R3 is connected to the VDD power supply. A bias voltage is supplied to the gate electrode of the NMOS transistor MN3 from the drain electrode of the NMOS transistor MN4.
When an input signal In and an inverted input signal Inb are input to the gate electrodes of the NMOS transistors MN1 and MN2, respectively, an output signal Out is output from the drain electrode of the NMOS transistor MN2, and an inverted output signal Outb is output from the drain electrode of the NMOS transistor MN1.
Generally, a plurality of stages of clock buffer circuits is connected in series, as shown in FIG. 2, for waveform shaping and timing adjustment of a clock signal. When an offset voltage is then present between outputs (at nodes A and A′ in FIG. 2) of a certain clock buffer circuit, the duty ratios of the output signal Out and the inverted output signal Outb vary, as shown in FIG. 2. Since the plurality of stages of clock buffer circuits is connected in series, the offset voltage may be accumulated and increased, so that the clock signal may disappear at some midpoint, at the worst. The larger the voltage gain of the clock buffer circuit is, the more noticeable this becomes. Since the voltage gain of the conventional clock buffer circuit in FIG. 1 changes proportional to the square root of the load resistances R1 and R2, variations of the load resistances become a main factor for variations of the voltage gain.
Patent Document 1 discloses means for compensating for the offset voltage as described above in SCFL (Source Coupled FET Logic) clock buffer circuits that use GaAs FETs. As an example of a first technique, providing capacitive coupling between stages and applying a direct current bias to a subsequent stage are disclosed. Further, as an example of a second technique, direct current feedback is provided between the stages of the SCFL clock buffer circuits, thereby suppressing the voltage gain and compensating for the offset voltage.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-5-268068